Welcome to the Open era of computing!

RISC-V is a free and open RISC ISA, driven through open collaboration.

Download Repo

What’s all the fuss about?

The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Free

Free

As it is open source, there is no need to pay for IP.

Simple

Simple

RISC-V is smaller than many commercial ISAs.

Stable

Stable

Base & First standard extensions are fixed, no updates needed.

Modular

Modular

RISC-V has a smaller standard base ISA.

Low-Power

Low Power

RISC-V ISA does not require any fees.

Extendible

Extensible

More functionality can be added as extensions.

Everyone Loves RISC-V

Nearly 300 of the biggest companies in the world are members of the RISC-V International orginaztion

Alibaba Cloud
Analog Devices
Arduio
Cadence
Google
Huawei
IBM
nVIDIA
Samsung
Siemens
Western Digital
Xilinix
Alibaba Cloud
Analog Devices
Arduio
Cadence
Google
Huawei
IBM
nVIDIA
Samsung
Siemens
Western Digital
Xilinix

Meet the team!

We’re 6 students at the Faculty of Engineering of Aswan University. Each one of us is excited about the Digital IC Design field. We started our journey with designing a Pipelined RV32I Core with a Hazard Unit and implementing it on two different FPGA boards.

Muhammad Mahmoud

Muhammad Mahmoud

Waseem Emile

Waseem Emile

Mustafa Amin

Mustafa Amin

Amir Mahdy

Amir Mahdy

Ahmed Hars

Ahmed Hars

Essam Kamaly

Essam Kamaly

RISC-Aswan Project

We Implemented and Deployed a Pipelined RISC-V RV32I Core on FPGA boards.

Single Cycle

01

Single-Cycle RV32I Core

Implemented a single-cycle RISC-V core based on RV32I ISA.

Pipelining

02

Pipelining

Increased throughput by implementing pipelined stages.

Hazard Unit

03

Hazard Unit

Solved pipelining problems by implementing a Hazard Unit.

Testbench

04

Testbench

Verified the functionality of each block in the design.

Synthesis

05

Synthesis

Verified RTL Schematic, Synthesis and Implementation.

Pipelining

06

Deploying on FPGA

Deployed the design to XC7A100T [ISE] and Basys-3 [Vivado] FPGA boards.

Verification

07

Verification

Verified boards functionality using test vectors and Vivado ILA.

Download Repo

More about RISC-V

Inspired enough to deep dive even more? Check out these resources.

Watch a video by the CEO of RISC-V-International

Visit the oficial sites to learn more

Get in touch

We’d love to get a feedback from you

Send us a Message!

required

required

required